Many of the conventional multi-threaded processors on the market today include hardware scheduling units that arbitrate issuing instructions to be executed among a plurality of active threads. The scheduling unit determines whether the next instruction for each thread has any dependencies that have not been resolved, and, among all threads having a next instruction with no unresolved dependencies, selects one thread and issues the next instruction from the thread. Such arbitration is conducted one instruction at a time.
For power reasons, it could be beneficial to resolve dependencies for multiple instructions at a time and then issue the multiple instructions in a batch. Such operation may be beneficial because the batch of instructions will typically be executed in a fewer number of clock cycles than if dependencies are resolved and instructions are issued one at a time. For example, latency related to fetching operands from a memory may be resolved at the beginning of the batch instead of spreading out the latency throughout the execution of the batch. This may allow for more efficient power savings techniques or allow more efficient use of resources by other active threads. Additional power savings may be realized by reducing the frequency that the scheduler executes (e.g., once per batch of instructions rather than once per instruction), utilizing low-power pipeline resources (e.g., register-file bypass, temporary pipeline storage, etc.), and other such power saving techniques.
One issue with issuing batch instructions in this manner, however, is that the batch of instructions may be interrupted after the batch has been scheduled for execution but before each instruction in the batch has been issued and committed by the associated pipeline. Interrupt routines may be necessary to implement breakpoints in a debugger, single-stepping through instructions in a debugger, floating point exceptions, instruction replays, memory addressing faults, memory breakpoints, tolerance of compiler bugs, cache misses, pre-emption, and other capabilities that require interruption of a batch of instructions. It will be appreciated that batches may be interrupted for reasons other than the service of interrupt routines; for example, batches may be interrupted to perform a memory access in response to a cache miss or to service a floating-point exception. Resources reserved for the batch of instructions (e.g., registers in a register file) may be allocated to execute the interrupt routine. Conventional processor architectures are not configured to implement schedulers that are capable of issuing batches of instructions while also enabling those batches of instructions to be interrupted. Thus, there is a need for addressing this issue and/or other issues associated with the prior art.